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- In article <NEWTNews.5451.829190655.rayon@pi-user.pi.net> rayon@pi.net writes:
- >
- >
- > Does someone know the exactly way for calculating dhrystones/mips/flops
- > for 680x0 processors??... It's very hard to find some info about this subject
-
- > even companies who sell motorola processors don't know!... So if someone can
-
- > help me!.. Please...
- >
- Can't help on the Dhrystones equations, but the definition of
- MIPS and FLOPS is such that a processor reference manual with timing
- diagrams (or similar data) for each instruction would be sufficient.
- Of course, for a machine which may have instructions with different
- timings you'll have to define what will be the average mix... After
- all, claiming MIPS rates for a 1-cycle register clear vs a 10-cycle
- memory increment would show a factor of 10 difference in MIPS rates.
-
- FLOPS is the same process, but using the floating point
- processor timings.
-
-
- Such calculations tend to be meaningless... A RISC
- architecture may have be 100MIPS but the nature of RISC is that you
- need more instructions to complete what a CISC processor does in one
- instruction. If, on average, it takes 5 RISC instructions to match
- one CISC operation, then that 100MIPS RISC is equivalent to a 20MIPS
- CISC.
-
- Comparisons across architectures aren't meaningful either...
- Last meaningful numbers I saw were reported in "VUPS" (VAX Units per
- second -- "unit" being the capability of the original 11/780).
-
- --
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- > wulfraed@netcom.com | Wulfraed Dennis Lee Bieber KD6MOG <
- > D.Bieber@GEnie.com | FurryMUCK and FurToonia <
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